As a typical example of visual inspection apparatus, an apparatus is known which, in order to detect defects in circuit patterns formed on a semiconductor wafer, obtains an image of a circuit pattern, compares the image with a reference image as the criterion of inspection, and extracts defects by difference between these images. In this relation, there is also a known method which uses as a reference image that just precedes the inspection image and such reference image is changed to the next one in turn. This method can be applied if the circuitry patterns to be inspected are identical and repeated in all the inspection images. In some cases circuitry patterns of chips produced on a semiconductor wafer are identical and repeated, while in other cases identical repeated circuitry patterns are produced on a chip. Comparison inspection in the former cases is called “die to die comparison inspection” and that in the latter cases is called “cell to cell comparison inspection”.
Such visual inspection apparatus obtains an image of an object under inspection and performs visual inspection or defect extraction by using an image processing apparatus. FIG. 17 is a functional block diagram showing a typical structure of an image processing unit of visual inspection apparatus for semiconductor wafer defect inspection.
In FIG. 17, a wafer 1702 that is an object under inspection is set in position on a wafer stage 1701. As the wafer stage is moved in X or Y directions, digital image data can be obtained by a sensor 1703 and an AD circuit 1704. The digital image input data is processed by an image processing unit 1705 to detect defects and the detected defect data is stored on an overall control computer 1706.
FIG. 18 shows semiconductor wafer top views for explaining a die to die comparison inspection system and a cell to cell comparison inspection system which are performed by the image processing unit 1705 of the visual inspection apparatus. Although both the term “die” and the term “chip” mean the same thing, the “die” is used herein when referring to the die to die comparison inspection; otherwise, the “chip” is used.
On the wafer 1702 to be inspected, a plurality of dice 1801 which have been fabricated in the manufacturing process are arranged in a grid. The die is a chip as individual semiconductor device. For simplifying purpose, chips n−1, n, n+1, and n+2 are enlarged in FIG. 18A. The apparatus obtains serial image data having a given width in the scanning direction. A die to die comparison inspection system is configured to compare neighboring chips in grid arrangement on the wafer 1702. For example, if an image of chip n is inspected, the image of the chip n−1 is used as a reference image. This comparison is repeated in turn as shown until the entire surface of the wafer is scanned, so that all the defects on the wafer can be detected.
On the other hand, the cell to cell comparison inspection system is configured to compare the repeated patterns which are called cells, like memory mats in one chip, as shown in FIG. 18B. For example, if an image of a particular cell on chip n is inspected, the image of the cell just preceding the particular cell on the same chip is used as the reference image for comparison.
By selecting the inspection condition to set the entire surface. Of memory mats on a wafer as inspection target area, not only the die to die comparison inspection but also the cell to cell comparison inspection can be performed.
The die to die comparison inspection system is applied to logic chips and the like. The cell to cell comparison inspection system is applied to memory chips and the like. Recently, a need for performing both of the cell to cell comparison inspection and the die to die comparison inspection simultaneously has arisen for mixed memory and logic chips.
FIG. 19 is a functional block diagram showing a configuration of the image processing unit 1705 of the visual inspection apparatus shown in FIG. 17, wherein the configuration is based on prior art that enables cell to cell and die to die hybrid comparison inspection.
Image data obtained through the sensor 1903 and the AD circuit 1904 is input to both a die to die comparison unit 1901 and a cell to cell comparison unit 1902. In the die to die comparison unit 1901, a chip delay circuit 1905 prepares the reference image of the chip just preceding a chip whose image data has now been obtained. A position correction and intensity correction circuit 1906 performs position correction to align the corresponding positions of the inspection image and the reference image, and compensates the difference in intensity between the two images. A differential image computing unit 1907 extracts the difference in intensity between the two images and a feature extraction computing unit 1908 detects feature quantities such as intensity, dimensions, and shape of defect extracted from intensity difference data and positional data. Such feature quantities are stored as defect data in the overall control computer 1909.
The cell to cell comparison unit 1902 is comprised of almost the same elements as the die to die comparison unit 1901, but differs from the die to die comparison unit 1901 in that it includes a cell delay circuit 1910 instead of the chip delay circuit 1905 to prepare the reference image of the cell just preceding a cell whose image data has now been obtained.
In the visual inspection apparatus, image signals are digitized and processed in a sequence of process steps comprising storing a captured die or cell inspection image and its reference image into a memory, comparing these two images, and extracting defects. However, because of a great amount of image data and insufficient processor capability, there has arisen a need to improve the speed of defect extraction.
Due to the improvement of processing capability of processors in recent years, an image processing apparatus of parallel data processing type employing a plurality of processor elements (abbreviated to PE in the relevant drawings) has been proposed (for example, refer to Japanese Patent Document 1).
FIG. 20 is a schematic diagram showing a conventional image processing apparatus configuration. Reference numeral 2001 denotes a data input block; 2002 denotes a process distribution block; 2003 denotes a status management block; 2004 denotes an output block; 2005 denotes a communications bus; and 2006 through 2009 denote processor elements (PEs (0) to (n)). In association with parallel processing of image data in this circuitry topology, a method for setting the sequence of distribution of input data to a plurality of processors is known. FIG. 21 is a diagram of operation sequence of the processors, which shows an example of data distribution to the four processors. Image data are distributed as unit image data to the processors in sequence so that the processors operate to process the unit image data in order. The first one unit image data of every one block consisting of four unit image data, for example, D1, D5, D9 of serial image data 2101 are distributed to and processed by the processor element PE (0). In FIG. 21, hatching area represents processing time of unit image data. Unit image data D2, D6, D10, etc. are distributed to the processor element PE (1). Unit image data D1, D7, etc. are distributed to the processor element PE (2). Unit image data D4, D8, etc. are distributed to the processor element PE (3).
In this parallel processing, the interval at which each processor element processes unit image data is determined by the processing time of unit image data and the throughput of input image. In general, the higher is the speed of capturing image input data, at the shorter intervals, unit image data are captured, and accordingly, the more processor elements are necessary.
When serial image data is partitioned into unit image data, input image adjustment or the like is performed by differential processing and position correction processing at the ends of unit image data. Consequently, there is a possibility that an area where it is impossible to perform operation processing is generated at the boundary between contiguous unit image data. As practical countermeasures against this problem, it is conceivable to divide unit image data at the boundary into a plurality of partitions so that partitions of contiguous image data are overlapped with each other (For example, refer to Japanese Patent Document 2). At the boundary between contiguous unit image data, for example, between unit image data D1 and D2 in FIG. 21, by overlapping the pixels of the area where it is impossible to perform operation processing and which is predicted from operation processing, it can prevent such an area from occurring.
By thus providing overlapped margins at the boundaries between contiguous unit image data and avoiding such an area where it is impossible to perform operation processing, all the unit image data can be inspected by die to die comparison inspection. In the case of cell to cell comparison inspection, however, data segments that cannot be inspected may take place as described below. Besides the inspection image, a reference image of the cell preceding the inspection cell is necessary in cell to cell comparison inspection. However, if, for example, the image of a cell to be inspected is positioned at the beginning of unit image data D2 which is processed by the processor element PE (1) in FIG. 21, the image of the preceding cell as the reference image does not exist in the data D2 and it becomes impossible to inspect this cell. Like this, image data distribution generates such an area that it is impossible to perform cell to cell comparison inspection.
[Japanese Patent Document 1]
JP-A No. 259434/1999 (p.6, FIG. 5)
[Japanese Patent Document 2]
JP-A No. 325162/1994 (p.3, FIG. 2)